LPDDR
Adapted from Wikipedia Β· Discoverer experience
LPDDR stands for Low-Power Double Data Rate. It is a special kind of memory called synchronous dynamic random-access memory that uses less power than regular memory. This makes it very useful for devices like smartphones, tablet computers, and laptops because saving power helps batteries last longer. In the past, people also called it Mobile DDR.
LPDDR is different from the regular kind of memory called DDR SDRAM. It is built in ways that work better for small devices. Instead of being placed in a separate part that can be removed, LPDDR is attached directly to the main board of the device. This saves space and makes the device work more efficiently.
Even though LPDDR and DDR memory have similar names like LPDDR4 and DDR4, they were developed separately. This means that the numbers do not mean they use the same technology. The rules for LPDDR are made and kept up by a group called the JEDEC Solid State Technology Association.
Bus width
LPDDR memory can work with smaller connections than regular memory used in computers. While regular memory usually connects with a 64-bit wide bus, LPDDR can also use 16-bit or 32-bit wide connections. This makes it useful for small devices like phones and tablets.
Some versions of LPDDR, marked with "E" or "X", allow the memory to work a bit faster than normal. Like regular memory, each new version of LPDDR usually makes data transfers faster, though there are some exceptions.
Generations
LPDDR(1)
The original low-power DDR, released in 2006, is a slightly changed form of DDR SDRAM to use less power.
It uses less power by lowering the voltage from 2.5 to 1.8 V. Other changes include saving power by refreshing less often in cold temperatures, using smaller memory areas, and having a special low-power mode that clears all data. This technology is used in devices like the iPhone 3GS, original iPad, Samsung Galaxy Tab 7.0 and Motorola Droid X.
LPDDR2
In 2009, a new standard called JESD209-2 was created for an improved low-power DDR interface. This version works differently from older DDR types but can handle various memory types.
It works at 1.2 V and uses special methods to manage power. Devices using LPDDR2 include the MacBook Air, iPhone 5S, iPhone 6, Nexus 10, Samsung Galaxy S4, and Microsoft Surface Pro 3 and 4.
LPDDR3
In May 2012, a new standard called JESD209-3 was published for LPDDR3. Compared to LPDDR2, LPDDR3 offers faster speeds, more data handling, better power efficiency, and higher memory capacity.
Products using LPDDR3 include the MacBook Air, iPhone 5S, iPhone 6, Nexus 10, Samsung Galaxy S4, and Microsoft Surface Pro 3 and 4. LPDDR3 became common in 2013, running at 800 MHz DDR (1600 MT/s).
LPDDR4
In March 2012, plans were made for LPDDR4, which was officially published in August 2014. Major changes include doubling the speed, changing how data is sent, and improving power efficiency.
LPDDR4 includes special methods to avoid problems with nearby memory areas. Samsung proposed LPDDR4X, which saves even more power by lowering the voltage further. SK Hynix announced LPDDR4X packages in January 2017.
LPDDR5
In February 2019, the standard for LPDDR5 was published. Samsung had working LPDDR5 chips as early as July 2018. LPDDR5 brings faster data rates, better power savings, and new ways to manage clocks and commands.
Devices supporting LPDDR5 include AMD Van Gogh, Intel Tiger Lake, Apple silicon (M1 Pro, M1 Max, M1 Ultra, M2 and A16 Bionic), Huawei Kirin 9000, and Snapdragon 888.
LPDDR5X
In July 2021, the standard for LPDDR5X was published, extending LPDDR5 with even faster speeds and better reliability. Samsung announced the first LPDDR5X DRAM in November 2021, which uses 20% less power than LPDDR5.
Micron announced that Mediatek had validated its LPDDR5X DRAM for Mediatek's Dimensity 9000 5G SoC in November 2021. SK Hynix announced "Low Power Double Data Rate 5 Turbo" (LPDDR5T) chips in January 2023, with a bandwidth of 9.6 Gbit/s.
Samsung announced LPDDR5X-10700 in April 2024, achieving 25% higher bandwidth, 30% higher capacity, and 25% improved power efficiency compared to previous LPDDR5X generations.
LPDDR6
In July 2025, the standard for LPDDR6 was published. LPDDR6 extends the speed to 10.6β14.4 Gbit/s per pin, narrows the control bus, and introduces new data handling methods.
| Gene- ration | Release year | Chip | Bus | Voltage (V) | ||||
|---|---|---|---|---|---|---|---|---|
| Clock rate (MHz) | Cycle time (ns) | Pre- fetch | Clock rate (MHz) | Transfer rate (MT/s) | Bandwidth (MB/s) | |||
| 1 | 2006 | 200 | 2n | 200 | 400 | 1 600 | 1.8 | |
| 1E | 266 | 266 | 533 | 2 132 | ||||
| 2 | 2009 | 200 | 4n | 400 | 800 | 3 200 | 1.2 1.8 | |
| 2E | 266 | 533 | 1067 | 4 268 | ||||
| 3 | 2012 | 200 | 8n | 800 | 1600 | 4 800 | 1.2 1.8 | |
| 3E | 266 | 1067 | 2133 | 8 532 | ||||
| 4 | 2014 | 200 | 16n | 1600 | 3200 | 12 800 | 1.1 1.8 | |
| 4X | 2017 | 266 | 2133 | 4267 | 17 068 | 0.6 1.1 1.8 | ||
| 5 | 2019 | 400 | 3200 | 6400 | 25 600 | 0.5 1.05 1.8 | ||
| 5X | 2021 | 666 | 5333 | 10667 | 42 668 | |||
| 6 | 2025 | 900 | 7200 | 14400 | 57 600 | 0.5 1.0 1.8 | ||
| Operation | β Rising clock β | β Falling clock β | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CA0 (RAS) | CA1 (CAS) | CA2 (WE) | CA3 | CA4 | CA5 | CA6 | CA7 | CA8 | CA9 | CA0 (RAS) | CA1 (CAS) | CA2 (WE) | CA3 | CA4 | CA5 | CA6 | CA7 | CA8 | CA9 | ||
| No operation | H | H | H | β | |||||||||||||||||
| Precharge all banks | H | H | L | H | H | β | |||||||||||||||
| Precharge one bank | H | H | L | H | L | β | BA0 | BA1 | BA2 | β | |||||||||||
| Preactive (LPDDR2-N only) | H | H | L | H | A30 | A31 | A32 | BA0 | BA1 | BA2 | A20 | A21 | A22 | A23 | A24 | A25 | A26 | A27 | A28 | A29 | |
| Burst terminate | H | H | L | L | β | ||||||||||||||||
| Read (AP=auto-precharge) | H | L | H | reserved | C1 | C2 | BA0 | BA1 | BA2 | AP | C3 | C4 | C5 | C6 | C7 | C8 | C9 | C10 | C11 | ||
| Write (AP=auto-precharge) | H | L | L | reserved | C1 | C2 | BA0 | BA1 | BA2 | AP | C3 | C4 | C5 | C6 | C7 | C8 | C9 | C10 | C11 | ||
| Activate (R0β14=Row address) | L | H | R8 | R9 | R10 | R11 | R12 | BA0 | BA1 | BA2 | R0 | R1 | R2 | R3 | R4 | R5 | R6 | R7 | R13 | R14 | |
| Activate (LPDDR2-N only) | L | H | A15 | A16 | A17 | A18 | A19 | BA0 | BA1 | BA2 | A5 | A6 | A7 | A8 | A9 | A10 | A11 | A12 | A13 | A14 | |
| Refresh all banks (LPDDR2-Sx only) | L | L | H | H | β | ||||||||||||||||
| Refresh one bank (round-robin addr.) | L | L | H | L | β | ||||||||||||||||
| Mode register read (MA0β7=addr.) | L | L | L | H | MA0 | MA1 | MA2 | MA3 | MA4 | MA5 | MA6 | MA7 | β | ||||||||
| Mode register write (OP0β7=data) | L | L | L | L | MA0 | MA1 | MA2 | MA3 | MA4 | MA5 | MA6 | MA7 | OP0 | OP1 | OP2 | OP3 | OP4 | OP5 | OP6 | OP7 | |
| First cycle (CS high) | Second cycle (CS low) | Operation | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CA5 | CA4 | CA3 | CA2 | CA1 | CA0 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 | |||
| L | L | L | L | L | L | β | No operation | |||||||
| H | L | L | L | L | L | 0 | OP4 | OP3 | OP2 | OP1 | 1 | Multi-purpose command | ||
| AB | H | L | L | L | L | β | BA2 | BA1 | BA0 | Precharge (AB: all banks) | ||||
| AB | L | H | L | L | L | β | BA2 | BA1 | BA0 | Refresh (AB: all banks) | ||||
| β | H | H | L | L | L | β | Self-refresh entry | |||||||
| BL | L | L | H | L | L | AP | C9 | β | BA2 | BA1 | BA0 | Write-1 (+CAS-2) | ||
| β | H | L | H | L | L | β | Self-refresh exit | |||||||
| 0 | L | H | H | L | L | AP | C9 | β | BA2 | BA1 | BA0 | Masked write-1 (+CAS-2) | ||
| β | H | H | H | L | L | β | Reserved | |||||||
| BL | L | L | L | H | L | AP | C9 | β | BA2 | BA1 | BA0 | Read-1 (+CAS-2) | ||
| C8 | H | L | L | H | L | C7 | C6 | C5 | C4 | C3 | C2 | CAS-2 | ||
| β | H | L | H | L | β | Reserved | ||||||||
| OP7 | L | L | H | H | L | MA5 | MA4 | MA3 | MA2 | MA1 | MA0 | Mode register write-1 and -2 MA: address, OP: data | ||
| OP6 | H | L | H | H | L | OP5 | OP4 | OP3 | OP2 | OP1 | OP0 | |||
| β | L | H | H | H | L | MA5 | MA4 | MA3 | MA2 | MA1 | MA0 | Mode register read (+CAS-2) | ||
| β | H | H | H | H | L | β | Reserved | |||||||
| R15 | R14 | R13 | R12 | L | H | R11 | R10 | R16 | BA2 | BA1 | BA0 | Activate-1 and -2 | ||
| R9 | R8 | R7 | R6 | H | H | R5 | R4 | R3 | R2 | R1 | R0 | |||
| β Rising clock β | β Falling clock β | Operation | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CA6 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 | CA6 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 | |||
| L | L | L | L | L | L | L | β | No operation | ||||||||
| H | L | L | L | L | L | L | β | Power-down entry | ||||||||
| L | H | L | L | L | L | L | β L β | Read FIFO | ||||||||
| H | H | L | L | L | L | L | β L β | Write FIFO | ||||||||
| L | L | H | L | L | L | L | β | Reserved | ||||||||
| H | L | H | L | L | L | L | β L β | Read DQ Calibration | ||||||||
| OP7 | H | H | L | L | L | L | OP6 | OP5 | OP4 | OP3 | OP2 | OP1 | OP0 | Multi-purpose command | ||
| OP7 | L | L | H | L | L | L | OP6 | OP5 | OP4 | OP3 | OP2 | OP1 | OP0 | Mode register write 2 | ||
| L | H | L | H | L | L | L | β | Self-refresh exit | ||||||||
| H | H | L | H | L | L | L | PD | DSE | β | Self-refresh entry | ||||||
| L | L | H | H | L | L | L | MA6 | MA5 | MA4 | MA3 | MA2 | MA1 | MA0 | Mode register read | ||
| H | L | H | H | L | L | L | MA6 | MA5 | MA4 | MA3 | MA2 | MA1 | MA0 | Mode register write 1 | ||
| L | H | H | H | L | L | L | AB | SB1 | SB0 | RFM | BG0 | BA1 | BA0 | Refresh | ||
| H | H | H | H | L | L | L | AB | β | BG1 | BG0 | BA1 | BA0 | Precharge | |||
| C5 | C4 | C3 | L | H | L | L | AP | C2 | C1 | BG1 | BG0 | BA1 | BA0 | Write 32 | ||
| WS_ FS | WS_ RD | WS_ WR | H | H | L | L | WXSB /B3 | WXSA | WRX | DC3 | DC2 | DC1 | DC0 | Column address select | ||
| C5 | C4 | C3 | C0 | L | H | L | AP | C2 | C1 | BG1 | BG0 | BA1 | BA0 | Masked Write | ||
| C5 | C4 | C3 | C0 | H | H | L | AP | C2 | C1 | BG1 | BG0 | BA1 | BA0 | Write | ||
| C5 | C4 | C3 | C0 | L | L | H | AP | C2 | C1 | BG1 | BG0 | BA1 | BA0 | Read | ||
| C5 | C4 | C3 | C0 | H | L | H | AP | C2 | C1 | BG1 | BG0 | BA1 | BA0 | Read 32 | ||
| R10 | R9 | R8 | R7 | L | H | H | R6 | R5 | R4 | R3 | R2 | R1 | R0 | Activate 2 | ||
| R17 | R16 | R15 | R14 | H | H | H | R13 | R12 | R11 | BG1 | BG0 | BA1 | BA0 | Activate 1 | ||
Bn = Burst address bit Cn = Column address bit Rn = Row address bit BAn = Bank address bit BGn = Bank group address bit AB = All banks (ignore BG & BA) AP = Auto-precharge | MAn = Mode register address bit OPn = Operation, or mode register data WS_xx = WCK synchronization WRX = Write X; do not transfer data, but fill with all-zero or all-one WXSA, WXSB = Write X select, value to be written PD = Power down DSE = Deep sleep enable |
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This article is a child-friendly adaptation of the Wikipedia article on LPDDR, available under CC BY-SA 4.0.
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