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LPDDR

Adapted from Wikipedia Β· Discoverer experience

A close-up view of a computer chip inside a Motorola Xoom tablet.

LPDDR stands for Low-Power Double Data Rate. It is a special kind of memory called synchronous dynamic random-access memory that uses less power than regular memory. This makes it very useful for devices like smartphones, tablet computers, and laptops because saving power helps batteries last longer. In the past, people also called it Mobile DDR.

Mobile DDR: Samsung K4X2G323PD-8GD8

LPDDR is different from the regular kind of memory called DDR SDRAM. It is built in ways that work better for small devices. Instead of being placed in a separate part that can be removed, LPDDR is attached directly to the main board of the device. This saves space and makes the device work more efficiently.

Even though LPDDR and DDR memory have similar names like LPDDR4 and DDR4, they were developed separately. This means that the numbers do not mean they use the same technology. The rules for LPDDR are made and kept up by a group called the JEDEC Solid State Technology Association.

Bus width

LPDDR memory can work with smaller connections than regular memory used in computers. While regular memory usually connects with a 64-bit wide bus, LPDDR can also use 16-bit or 32-bit wide connections. This makes it useful for small devices like phones and tablets.

Some versions of LPDDR, marked with "E" or "X", allow the memory to work a bit faster than normal. Like regular memory, each new version of LPDDR usually makes data transfers faster, though there are some exceptions.

Generations

LPDDR(1)

The original low-power DDR, released in 2006, is a slightly changed form of DDR SDRAM to use less power.

It uses less power by lowering the voltage from 2.5 to 1.8 V. Other changes include saving power by refreshing less often in cold temperatures, using smaller memory areas, and having a special low-power mode that clears all data. This technology is used in devices like the iPhone 3GS, original iPad, Samsung Galaxy Tab 7.0 and Motorola Droid X.

LPDDR2

In 2009, a new standard called JESD209-2 was created for an improved low-power DDR interface. This version works differently from older DDR types but can handle various memory types.

It works at 1.2 V and uses special methods to manage power. Devices using LPDDR2 include the MacBook Air, iPhone 5S, iPhone 6, Nexus 10, Samsung Galaxy S4, and Microsoft Surface Pro 3 and 4.

LPDDR3

In May 2012, a new standard called JESD209-3 was published for LPDDR3. Compared to LPDDR2, LPDDR3 offers faster speeds, more data handling, better power efficiency, and higher memory capacity.

Products using LPDDR3 include the MacBook Air, iPhone 5S, iPhone 6, Nexus 10, Samsung Galaxy S4, and Microsoft Surface Pro 3 and 4. LPDDR3 became common in 2013, running at 800 MHz DDR (1600 MT/s).

LPDDR4

Samsung K4P4G154EC-FGC1 4Β Gbit LPDDR2 chip

In March 2012, plans were made for LPDDR4, which was officially published in August 2014. Major changes include doubling the speed, changing how data is sent, and improving power efficiency.

LPDDR4 includes special methods to avoid problems with nearby memory areas. Samsung proposed LPDDR4X, which saves even more power by lowering the voltage further. SK Hynix announced LPDDR4X packages in January 2017.

LPDDR5

In February 2019, the standard for LPDDR5 was published. Samsung had working LPDDR5 chips as early as July 2018. LPDDR5 brings faster data rates, better power savings, and new ways to manage clocks and commands.

Devices supporting LPDDR5 include AMD Van Gogh, Intel Tiger Lake, Apple silicon (M1 Pro, M1 Max, M1 Ultra, M2 and A16 Bionic), Huawei Kirin 9000, and Snapdragon 888.

LPDDR5X

In July 2021, the standard for LPDDR5X was published, extending LPDDR5 with even faster speeds and better reliability. Samsung announced the first LPDDR5X DRAM in November 2021, which uses 20% less power than LPDDR5.

Micron announced that Mediatek had validated its LPDDR5X DRAM for Mediatek's Dimensity 9000 5G SoC in November 2021. SK Hynix announced "Low Power Double Data Rate 5 Turbo" (LPDDR5T) chips in January 2023, with a bandwidth of 9.6 Gbit/s.

Samsung announced LPDDR5X-10700 in April 2024, achieving 25% higher bandwidth, 30% higher capacity, and 25% improved power efficiency compared to previous LPDDR5X generations.

LPDDR6

In July 2025, the standard for LPDDR6 was published. LPDDR6 extends the speed to 10.6–14.4 Gbit/s per pin, narrows the control bus, and introduces new data handling methods.

Comparison of LPDDR SDRAM generations
Gene-
ration
Release
year
ChipBusVoltage
(V)
Clock rate
(MHz)
Cycle time
(ns)
Pre-
fetch
Clock rate
(MHz)
Transfer rate
(MT/s)
Bandwidth
(MB/s)
120062002n2004001 6001.8
1E2662665332 132
220092004n4008003 200
1.2
1.8
2E26653310674 268
320122008n80016004 800
1.2
1.8
3E266106721338 532
4201420016n1600320012 800
1.1
1.8
4X20172662133426717 068
0.6
1.1
1.8
520194003200640025 600
0.5
1.05
1.8
5X202166653331066742 668
6202590072001440057 600
0.5
1.0
1.8
LPDDR2/LPDDR3 command encoding
Operationβ†— Rising clock β†—β†˜ Falling clock β†˜
CA0
(RAS)
CA1
(CAS)
CA2
(WE)
CA3CA4CA5CA6CA7CA8CA9CA0
(RAS)
CA1
(CAS)
CA2
(WE)
CA3CA4CA5CA6CA7CA8CA9
No operationHHHβ€”
Precharge all banksHHLHHβ€”
Precharge one bankHHLHLβ€”BA0BA1BA2β€”
Preactive (LPDDR2-N only)HHLHA30A31A32BA0BA1BA2A20A21A22A23A24A25A26A27A28A29
Burst terminateHHLLβ€”
Read (AP=auto-precharge)HLHreservedC1C2BA0BA1BA2APC3C4C5C6C7C8C9C10C11
Write (AP=auto-precharge)HLLreservedC1C2BA0BA1BA2APC3C4C5C6C7C8C9C10C11
Activate (R0–14=Row address)LHR8R9R10R11R12BA0BA1BA2R0R1R2R3R4R5R6R7R13R14
Activate (LPDDR2-N only)LHA15A16A17A18A19BA0BA1BA2A5A6A7A8A9A10A11A12A13A14
Refresh all banks (LPDDR2-Sx only)LLHHβ€”
Refresh one bank (round-robin addr.)LLHLβ€”
Mode register read (MA0–7=addr.)LLLHMA0MA1MA2MA3MA4MA5MA6MA7β€”
Mode register write (OP0–7=data)LLLLMA0MA1MA2MA3MA4MA5MA6MA7OP0OP1OP2OP3OP4OP5OP6OP7
LPDDR4 command encoding:β€Š151β€Š
First cycle (CS high)Second cycle (CS low)Operation
CA5CA4CA3CA2CA1CA0CA5CA4CA3CA2CA1CA0
LLLLLLβ€”No operation
HLLLLL0OP4OP3OP2OP11Multi-purpose command
ABHLLLLβ€”BA2BA1BA0Precharge (AB: all banks)
ABLHLLLβ€”BA2BA1BA0Refresh (AB: all banks)
β€”HHLLLβ€”Self-refresh entry
BLLLHLLAPC9β€”BA2BA1BA0Write-1 (+CAS-2)
β€”HLHLLβ€”Self-refresh exit
0LHHLLAPC9β€”BA2BA1BA0Masked write-1 (+CAS-2)
β€”HHHLLβ€”Reserved
BLLLLHLAPC9β€”BA2BA1BA0Read-1 (+CAS-2)
C8HLLHLC7C6C5C4C3C2CAS-2
β€”HLHLβ€”Reserved
OP7LLHHLMA5MA4MA3MA2MA1MA0Mode register write-1 and -2
MA: address, OP: data
OP6HLHHLOP5OP4OP3OP2OP1OP0
β€”LHHHLMA5MA4MA3MA2MA1MA0Mode register read (+CAS-2)
β€”HHHHLβ€”Reserved
R15R14R13R12LHR11R10R16BA2BA1BA0Activate-1 and -2
R9R8R7R6HHR5R4R3R2R1R0
LPDDR5 command encoding
β†— Rising clock β†—β†˜ Falling clock β†˜Operation
CA6CA5CA4CA3CA2CA1CA0CA6CA5CA4CA3CA2CA1CA0
LLLLLLLβ€”No operation
HLLLLLLβ€”Power-down entry
LHLLLLLβ€” L β€”Read FIFO
HHLLLLLβ€” L β€”Write FIFO
LLHLLLLβ€”Reserved
HLHLLLLβ€” L β€”Read DQ Calibration
OP7HHLLLLOP6OP5OP4OP3OP2OP1OP0Multi-purpose command
OP7LLHLLLOP6OP5OP4OP3OP2OP1OP0Mode register write 2
LHLHLLLβ€”Self-refresh exit
HHLHLLLPDDSEβ€”Self-refresh entry
LLHHLLLMA6MA5MA4MA3MA2MA1MA0Mode register read
HLHHLLLMA6MA5MA4MA3MA2MA1MA0Mode register write 1
LHHHLLLABSB1SB0RFMBG0BA1BA0Refresh
HHHHLLLABβ€”BG1BG0BA1BA0Precharge
C5C4C3LHLLAPC2C1BG1BG0BA1BA0Write 32
WS_
FS
WS_
RD
WS_
WR
HHLLWXSB
/B3
WXSAWRXDC3DC2DC1DC0Column address select
C5C4C3C0LHLAPC2C1BG1BG0BA1BA0Masked Write
C5C4C3C0HHLAPC2C1BG1BG0BA1BA0Write
C5C4C3C0LLHAPC2C1BG1BG0BA1BA0Read
C5C4C3C0HLHAPC2C1BG1BG0BA1BA0Read 32
R10R9R8R7LHHR6R5R4R3R2R1R0Activate 2
R17R16R15R14HHHR13R12R11BG1BG0BA1BA0Activate 1
Bn = Burst address bit
Cn = Column address bit
Rn = Row address bit
BAn = Bank address bit
BGn = Bank group address bit
AB = All banks (ignore BG & BA)
AP = Auto-precharge
MAn = Mode register address bit
OPn = Operation, or mode register data
WS_xx = WCK synchronization
WRX = Write X; do not transfer data, but fill with all-zero or all-one
WXSA, WXSB = Write X select, value to be written
PD = Power down
DSE = Deep sleep enable

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This article is a child-friendly adaptation of the Wikipedia article on LPDDR, available under CC BY-SA 4.0.

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